Statistical Information Processing

Application-level tolerance to approximations is commonly exploited in approximate computing research today. This paper focuses on how this can be leveraged towards tolerance to nonidealities in circuit/device fabrics (variations, defects). Errors due to the computation fabrics can arise either due to reduction of design margins, e.g., to push the limits of energy efficiency and throughput in CMOS, or due to intrinsically-high defect rates and variability in late-CMOS and non-mature post-CMOS fabrics. An architectural framework referred to as statistical information processing is presented, whereby algorithmic approaches, both explicit and implicit, are employed with the objective of maximizing this leverage while meeting application-level requirements. To realize this objective, this paper highlights: (i) data-error tolerant accelerators based on techniques from statistical signal processing and machine learning; (ii) effective management of catastrophic control errors; (iii) appropriate programming models; and (iv) accurate microarchitectural and architectural error modeling based on realistic device-level fault models.